1. Field of the Invention
The present invention relates to creating planar surfaces on a substrate. More particularly, the present invention relates to global planarization methods and apparatuses designed to produce a microscopically smooth surface on a semiconductor wafer.
2. Background of Related Art
Integrated circuits are typically constructed by depositing layers of predetermined materials to form the circuit components on a wafer shaped semiconductor substrate. The formation of the circuit components in each layer produces a rough, or planar topography on the surface of the wafer. The resulting nonplanar surface must be made smooth and planar to provide a proper surface for the formation of subsequent layers of the integrated circuitry. Planarization of the outermost surface of the wafer is performed locally over small regions of the wafers and globally over the entire surface. Typically, a layer of oxide is deposited over the exposed circuit layer to provide an insulating layer for the circuit and to locally planarize regions. A thicker layer is then deposited on top of the insulating layer to provide a surface that can be globally planarized without damaging the deposited circuitry. The thick outer layer is generally composed of an oxide or a polymer material. Spin coating is a commonly used technique to form the thick polymer layers on a wafer. Thick oxide layers can be deposited using conventional deposition techniques. While those techniques are useful in producing uniform thickness layers, neither technique is particularly effective at producing a planar surface when applied to a nonplanar surface. As such, additional surface preparation is generally required prior to forming additional circuit layers on the wafer.
Conventional methods for globally planarizing the outermost surface of the wafer include chemical etching and chemical mechanical polishing (CMP) of the surface. In chemical etching, a thick layer is produced over the circuit layer as described above and the thick layer is chemically etched back to planarize the surface. Global planarization by this technique is iterative in that following the etching step, if the surface was not sufficiently smooth, a new layer of polymer or oxide must be formed and subsequently etched back. This process is time consuming, lacks predictability due to the iterative procedure for obtaining a planarized surface and consumes significant amounts of oxides and/or polymers in the process.
In the CMP technique, a reactive chemical slurry is used in conjunction with a polishing pad to planarize the surface of the wafer. Two problems associated with the CMP techniques are that the chemicals may become unevenly distributed in the pad, and particulates removed from the substrate during the polishing process may become lodged in the pad, both of which result in nonuniformity in the substrate surface. As a result, CMP techniques are generally less desirable since the process is often time consuming, exposes the wafers to aggressive chemicals and may not yield the desired results in terms of final surface quality.
An alternative to the above techniques is the use of a press planarization technique to globally planarize the surface of the wafer. In global press planarization, a deformable layer is deposited on the surface of the wafer containing the circuit components by conventional processes known in the art, such as by spin coating. The surface of the deformable layer, which is usually an uncured polymer, is pressed against a surface having surface characteristics which are desired for the surface of the wafer. The deformable layer is typically then cured while under pressure to harden the deformable layer to produce a planarized outermost surface of the desired surface quality.
Apparatuses used to perform the global press planarization are known in the art, such as those disclosed in U.S. Pat. No. 5,434,107 to Paranjpe. A problem with those global planarization apparatuses is encountered due to the need to apply a uniform force to the deformable layers while providing an apparatus to be used in production scale operations. For instance, the pressing surfaces of such apparatuses contain holes to allow loading fingers to pass through the surface and lift the wafer; these holes will invariably lead to nonuniform pressure distributions across the surface of the wafer and in the surface of the deformable layer. Additionally, the force used to planarize is applied directly to the surface of the wafer; therefore, any nonuniformities in the application of the force will be directly propagated to the surface layer resulting in less than optimal surface characteristics. The Paranjpe patent suggests a possible solution to the potential direct application of a nonuniform force through the use of direct fluid contact with the wafer and the application of the planarizing force to the wafer by pressurizing the fluid. However, the use of pressurized fluid contact results in substantial complications involved with handling pressurized fluid, as well as exposing the wafer to the fluid and the necessary addition of drying steps to the process. The aforementioned difficulties result in increased throughput time, require precise production controls and a higher potential for damage to the wafers during processing.
It is therefore an object of the present invention to provide a method and an apparatus for global process planarization of the surface layer of a semiconductor wafer that is conducive to automated handling and provides for a uniform distribution of force to planarize the surface.